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项目作者： Soham-coder

项目描述 ：
ROCC accelerator ISA based neuroSynapse
高级语言： SystemVerilog
项目地址: git://github.com/Soham-coder/ROCC_based_neurosynapse.git
创建时间： 2021-04-25T06:33:18Z
项目社区：https://github.com/Soham-coder/ROCC_based_neurosynapse
开源协议：
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ROCC_based_neurosynapse

Instructions to run simulations



#### Run 1st operation design + TB
cd run_scripts chmod +x run_operation1.sh ./run_operation1.sh


diff - o/p log "log_operation1.txt" will be created inside "log" directory - operation1 does "result = a*b+c*d", where result,a,b,c,d are all 32 bit IEEE floating pt. numbers

#### Run 2nd operation design + TB
cd run_scripts chmod +x run_operation2.sh ./run_operation2.sh


diff - o/p log "log_operation2.txt" will be created inside "log" directory - operation2 does "result = a/b+c/d", where result,a,b,c,d are all 32 bit IEEE floating pt. numbers

#### Run 3rd operation design + TB
cd run_scripts chmod +x run_operation3.sh ./run_operation3.sh


diff - o/p log "log_operation3.txt" will be created inside "log" directory

#### Run ROCC_accel + TB
cd run_scripts chmod +x run_rocc_accel.sh ./run_rocc_accel.sh


diff - o/p log "log_rocc_accel.txt" will be created inside "log" directory



ROCC Instruction format

ROCC_instruction_format

  1. So we will have the signal inst[31:0] going to the ROCC accelerator
  3. inst[31:25] = funct7
  4. inst[24:20] = rs2
  5. inst[19:15] = rs1
  6. inst[14] = xd
  7. inst[13] = xs1
  8. inst[12] = xs2
  9. inst[11:7] = rd
  10. inst[6:5] = opcode 
  12. According to format above
  15. opcode = 0 (For Neurosynapse accelerator, only 2 bits are sent)
  16. xd = 0 (ROCC core will expect nothing in return, all return values will be stored in local physical register file)
  17. xs1 = 1 (ROCC core will provide rs1)
  18. xs2 = 1 (ROCC core will provide rs2)
  19. rs1 = 5'b00000 (fixed register address from which all rs1 operands will come)
  20. rs2 = 5'b00001 (fixed register address from which all rs2 operands will come)
  21. rd = (destination register address of local reg file taken as it is) - 5 bits so 32 addresses possible
  22. funct7 = operation1/operation2/operation3
  23.          operation1 = 7'b0000_001
  24.          operation2 = 7'b0000_010
  25.          operation3 = 7'b0000_011
  26.          operation4 = 7'b0000_100
  27.          operation5 = 7'b0000_101

ROCC Request Interface

ROCC_request_interface

  1. Supply the following from ROCC_core (TB in our case)
  2. inst[31:0] = ROCC_instruction
  3. rs1[63:0]
  4. - rs1[63:32] = 1st_operand
  5. - rs2[31:0] = 2nd_operand
  6. rs2[63:0]
  7. - rs2[63:32] = 3rd_operand
  8. - rs2[31:0] = 4th_operand  
  10. valid should be held high while giving instruction and held stable until ready (coming from ROCC_accel)
  11. is high.
  13. When (valid && ready === 1), complete request will be accepted and ready will be made low until ROCC_accel completes 
  14. processing present instruction and goes for next one

ROCC Response Interface

ROCC_reponse_interface

  1. Nothing to supply back to the core, write 
  2. the result [31:0] value to register address specified by rd=inst[11:7]
  1. Then how to get the value written to local register file if there is no reg_read stage or spec does not allow it?
  3. Approach will be -
  4. Get it from TB the register value written to by previous operation. 
  5. -> Store previous "rd" from previous sent inst[31:5]
  6. -> Tap Register_File[rd] of DUT in TB when operation of rocc_accel completes
  7. -> Send this value along with others in next inst[31:5]
rocc_sumaccel_1647812315589.pdf